低电平

[dī diàn píng]

汉英

网络释义

na.
1.
low level

例句

释义:
全部全部,low levellow level,LOWLOW,VOLVOL,VILVIL
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1.
A transition in a logic signal from a logic high to a logic low is referred to as a falling edge.
逻辑信号从高电平到低电平的转换被称为下降沿。
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2.
The sinking digital output controls the line by using a transistor to leave the line high (at +V) or to ground the line to 0 V.
Sinking数字输出通过三极管来控制连接线上的电平为高电平（+V）或是低电平（0V）。
article.yeeyan.org
3.
Shielding may also be applied to a conductor carrying a high level test voltage to prevent interference with nearby low level circuits.
承载高测试电压的导体也应该采用屏蔽，以防止与邻近的低电平电路发生干扰。
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4.
The TRST pin is an optional active- low reset to the test logic - usually asynchronous , but sometimes synchronous , depending on the chip .
TRST引脚是一个可选的相对待测逻辑低电平有效的复位开关--通常是异步的，但有时也是同步的，依芯片而定。
us.zph981011.xyz
5.
The auxiliary device checks the 'data' line. If the line is inactive, the controller receives data from the system.
设备检查数据线，如果是低电平，那么控制器从系统接收数据。
blog.sina.com.cn
6.
Subsequently, after a predetermined time-out-active period, it goes back to the high state in an active-low reset.
随后，在预先设定的有效延时时间后，其从低电平有效复位回到高电平状态。
group.ednchina.com
7.
the driving signals of the electromagnetic valve include low level signals, high level signals and digital pulse signals.
电磁阀的驱动信号为低电平、高电平和数字脉冲信号三种驱动信号。
ip.com
8.
This means that high-speed, high-level circuits can "talk to" low-levelcircuits through the common impedance of the negative supply LINE.
这意味着：高速，高电平的电路，通过负压供电线，可以和低电平的电路“对话”。
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9.
If this output does not switch between H and L anymore a hard-ware reset is produced and the processor is initialized again.
如这个输出不再在高电平和低电平间作切换，硬件复位就会产生，并将处理器再次初始化。
us.zph981011.xyz
10.
The auxiliary device checks the 'clock' line. If the line is inactive, output from the device is not allowed.
辅助设备（指键盘）检查时钟线，如果时低电平，禁止发送数据。
hi.baidu.com